Key Features

Power supply (Normal)

VDD & VDDQ = 1.2V ± 0.06V

VPP = 2.5V +0.25V / -0.125V

VDDSPD = 2.5V (2.25V to 3.6V)

• JEDEC RDIMM Form factor

• Density

32GB (2Rank, x8)

• Data transfer rates:

PC4-2666 (CL19)

• Supports ECC error detection and correction

• 1.2V pseudo open-drain I/O

• Burst Length (BL) :8 and 4 with Burst Chop (BC)

• Bi-directional, differential data strobe (DQS and /DQS)

• DLL aligns DQ and DQS transition with CK transition

• Double- data-rate architecture; two data transfers per clock cycle

• On Die Termination using ODT pin

• Self refresh mode / Low-power auto refresh (LPASR) / Temperature controlled refresh (TCR)

• Array Configuration : 8 banks (x16) 2 groups of 4 banks

• 8n-bit prefetch architecture

• Tc of 0°C to 95°C

64ms, 8192-cycle refresh at 0°C to 85°C / 32ms, 8192-cycle refresh at 85°C to 95°C

• Lead- free and Halogen-free products are RoHS Compliant