Key features
ARM+FPGA Synergy: ARM handles application software; the FPGA enables hardware acceleration and precise timing control, solving compute and latency bottlenecks.
Versatility and Flexibility: The programmable SOC allows flexible reconfiguration to meet diverse lab needs—from communications to image processing and industrial control.
High-Speed Data Links: 2×10G optical ports and 14 GTX lanes support real-time, high-volume data transfer
Stable & Reliable: Operates from -40 °C to 85 °C with 5‑14 V input. Built-in protection ensures stability in harsh environments (aerospace, defense).
Specifications
|
Functional Unit |
Specific Parameters |
|
SOC FPGA |
XC7Z100-FFG900I, Dual-core ARM Cortex-A9 + FPGA |
|
QSPI NOR FLASH |
QSPI-interface NOR FLASH with a capacity of 1 Gb |
|
PS DDR |
PS-side: 2 pieces of DDR3, total 1GB capacity, 1866M×32bit data bandwidth |
|
PL DDR |
PL-side: 4 pieces of DDR3, total 2GB capacity, 1866M×64bit data bandwidth |
|
Ethernet |
1 RGMII Ethernet port, 10/100/1000Mbps auto-negotiation, RJ45 connector |
|
Debug UART |
2 PS-side debug UART ports, TYPE-C connector |
|
CAN |
2 PS-side CAN interfaces, 1 PL-side CAN interface, routed via J30J connector (internal 120Ω termination resistors populated) |
|
RS485 Interface |
2 RS485 interfaces, routed via J30J connector |
|
LVDS Interface |
LVDS interface includes 32 Tx and 8 Rx channels, routed via dual-layer RJ45 connector |
|
RS422 Interface |
RS422 interface includes 4 Tx and 4 Rx channels, routed via J30J connector |
|
GPIO |
8 reserved PL-side GPIOs, 3.3V, routed via J30J connector |
|
JTAG Interface |
Routed via 2x7 simple box header connector |
|
Optical Ports |
2×10G optical ports, routed via SFP+cage |
|
GTX |
14 Lanes, GTX signals routed via SMA connectors |
|
Power Supply |
Input compatible with 5V–14V, recommended supply voltage 12VDC |
|
Dimensions & Weight |
31.4 x 21.4 x 13.5 cm 2.72kg |
